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Yang is currently a senior undergraduate at the University of Arkansas majoring in Computer Engineering. Over the past years, he has gained experience in VHDL, Verilog, C/C++, Java, Python, and SQL. He is currently a research assistant at the University of Arkansas in Dr. Jia Di’s Trulogic Lab which interests in trustable digital hardware design and analysis at all levels. During this time, valuable skills have been developed in gate schematics and layouts designed in Cadence. One of Yang’s interest is exploring other aspects of integrated circuits through related projects.